\UART_1:BUART:tx_state_0\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
50.633 MHz |
19.750 |
13021.917 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell11 |
U(1,1) |
1 |
\UART_1:BUART:tx_state_0\ |
\UART_1:BUART:tx_state_0\/clock_0 |
\UART_1:BUART:tx_state_0\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_0\ |
\UART_1:BUART:tx_state_0\/q |
\UART_1:BUART:counter_load_not\/main_1 |
6.670 |
macrocell2 |
U(0,4) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_1 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.290 |
datapathcell2 |
U(0,4) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_state_2\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
58.163 MHz |
17.193 |
13024.474 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell12 |
U(1,4) |
1 |
\UART_1:BUART:tx_state_2\ |
\UART_1:BUART:tx_state_2\/clock_0 |
\UART_1:BUART:tx_state_2\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_2\ |
\UART_1:BUART:tx_state_2\/q |
\UART_1:BUART:counter_load_not\/main_3 |
4.113 |
macrocell2 |
U(0,4) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_3 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.290 |
datapathcell2 |
U(0,4) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:rx_state_0\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
60.172 MHz |
16.619 |
13025.048 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell15 |
U(0,0) |
1 |
\UART_1:BUART:rx_state_0\ |
\UART_1:BUART:rx_state_0\/clock_0 |
\UART_1:BUART:rx_state_0\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:rx_state_0\ |
\UART_1:BUART:rx_state_0\/q |
\UART_1:BUART:rx_counter_load\/main_1 |
4.410 |
macrocell5 |
U(0,0) |
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/main_1 |
\UART_1:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
2.249 |
count7cell |
U(0,0) |
1 |
\UART_1:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_state_2\/q |
\UART_1:BUART:sTX:TxSts\/status_0 |
60.924 MHz |
16.414 |
13025.253 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell12 |
U(1,4) |
1 |
\UART_1:BUART:tx_state_2\ |
\UART_1:BUART:tx_state_2\/clock_0 |
\UART_1:BUART:tx_state_2\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_2\ |
\UART_1:BUART:tx_state_2\/q |
\UART_1:BUART:tx_status_0\/main_4 |
7.126 |
macrocell3 |
U(1,1) |
1 |
\UART_1:BUART:tx_status_0\ |
\UART_1:BUART:tx_status_0\/main_4 |
\UART_1:BUART:tx_status_0\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:tx_status_0\ |
\UART_1:BUART:tx_status_0\/q |
\UART_1:BUART:sTX:TxSts\/status_0 |
4.188 |
statusicell1 |
U(1,1) |
1 |
\UART_1:BUART:sTX:TxSts\ |
|
SETUP |
0.500 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_state_1\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
61.463 MHz |
16.270 |
13025.397 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell10 |
U(0,4) |
1 |
\UART_1:BUART:tx_state_1\ |
\UART_1:BUART:tx_state_1\/clock_0 |
\UART_1:BUART:tx_state_1\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_1\ |
\UART_1:BUART:tx_state_1\/q |
\UART_1:BUART:counter_load_not\/main_0 |
3.190 |
macrocell2 |
U(0,4) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_0 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.290 |
datapathcell2 |
U(0,4) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
63.633 MHz |
15.715 |
13025.952 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell2 |
U(0,4) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
0.190 |
Route |
|
1 |
\UART_1:BUART:tx_bitclk_enable_pre\ |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART_1:BUART:counter_load_not\/main_2 |
3.695 |
macrocell2 |
U(0,4) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_2 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.290 |
datapathcell2 |
U(0,4) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:rx_state_2\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
64.181 MHz |
15.581 |
13026.086 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell18 |
U(0,0) |
1 |
\UART_1:BUART:rx_state_2\ |
\UART_1:BUART:rx_state_2\/clock_0 |
\UART_1:BUART:rx_state_2\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:rx_state_2\ |
\UART_1:BUART:rx_state_2\/q |
\UART_1:BUART:rx_counter_load\/main_3 |
3.372 |
macrocell5 |
U(0,0) |
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/main_3 |
\UART_1:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
2.249 |
count7cell |
U(0,0) |
1 |
\UART_1:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
\UART_1:BUART:sTX:TxSts\/status_0 |
64.931 MHz |
15.401 |
13026.266 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell1 |
U(1,1) |
1 |
\UART_1:BUART:sTX:TxShifter:u0\ |
\UART_1:BUART:sTX:TxShifter:u0\/clock |
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
3.580 |
Route |
|
1 |
\UART_1:BUART:tx_fifo_empty\ |
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
\UART_1:BUART:tx_status_0\/main_3 |
3.783 |
macrocell3 |
U(1,1) |
1 |
\UART_1:BUART:tx_status_0\ |
\UART_1:BUART:tx_status_0\/main_3 |
\UART_1:BUART:tx_status_0\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:tx_status_0\ |
\UART_1:BUART:tx_status_0\/q |
\UART_1:BUART:sTX:TxSts\/status_0 |
4.188 |
statusicell1 |
U(1,1) |
1 |
\UART_1:BUART:sTX:TxSts\ |
|
SETUP |
0.500 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:pollcount_1\/q |
\UART_1:BUART:sRX:RxShifter:u0\/route_si |
65.283 MHz |
15.318 |
13026.349 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell21 |
U(0,1) |
1 |
\UART_1:BUART:pollcount_1\ |
\UART_1:BUART:pollcount_1\/clock_0 |
\UART_1:BUART:pollcount_1\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:pollcount_1\ |
\UART_1:BUART:pollcount_1\/q |
\UART_1:BUART:rx_postpoll\/main_0 |
4.957 |
macrocell6 |
U(0,1) |
1 |
\UART_1:BUART:rx_postpoll\ |
\UART_1:BUART:rx_postpoll\/main_0 |
\UART_1:BUART:rx_postpoll\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_postpoll\ |
\UART_1:BUART:rx_postpoll\/q |
\UART_1:BUART:sRX:RxShifter:u0\/route_si |
2.291 |
datapathcell3 |
U(0,1) |
1 |
\UART_1:BUART:sRX:RxShifter:u0\ |
|
SETUP |
3.470 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_state_1\/q |
\UART_1:BUART:sTX:TxSts\/status_0 |
65.604 MHz |
15.243 |
13026.424 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell10 |
U(0,4) |
1 |
\UART_1:BUART:tx_state_1\ |
\UART_1:BUART:tx_state_1\/clock_0 |
\UART_1:BUART:tx_state_1\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_1\ |
\UART_1:BUART:tx_state_1\/q |
\UART_1:BUART:tx_status_0\/main_0 |
5.955 |
macrocell3 |
U(1,1) |
1 |
\UART_1:BUART:tx_status_0\ |
\UART_1:BUART:tx_status_0\/main_0 |
\UART_1:BUART:tx_status_0\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:tx_status_0\ |
\UART_1:BUART:tx_status_0\/q |
\UART_1:BUART:sTX:TxSts\/status_0 |
4.188 |
statusicell1 |
U(1,1) |
1 |
\UART_1:BUART:sTX:TxSts\ |
|
SETUP |
0.500 |
Clock |
|
|
|
|
Skew |
0.000 |
|