Static Timing Analysis

Project : EEPROM Char Gen
Build Time : 02/21/18 15:44:31
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 58.336 MHz
UART_1_IntClock CyMASTER_CLK 76.677 kHz 76.677 kHz 50.633 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 58.336 MHz 17.142 24.525
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 6.288
macrocell6 U(0,1) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.291
datapathcell3 U(0,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 87.474 MHz 11.432 30.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.179
macrocell21 U(0,1) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 87.474 MHz 11.432 30.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.179
macrocell22 U(0,1) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 93.423 MHz 10.704 30.963
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.451
macrocell18 U(0,0) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 93.423 MHz 10.704 30.963
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.451
macrocell23 U(0,0) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 93.475 MHz 10.698 30.969
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.445
macrocell15 U(0,0) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 93.475 MHz 10.698 30.969
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.445
macrocell24 U(0,0) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 50.633 MHz 19.750 13021.917
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,1) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 6.670
macrocell2 U(0,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.290
datapathcell2 U(0,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 58.163 MHz 17.193 13024.474
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,4) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 4.113
macrocell2 U(0,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.290
datapathcell2 U(0,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 60.172 MHz 16.619 13025.048
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,0) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 4.410
macrocell5 U(0,0) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.249
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:TxSts\/status_0 60.924 MHz 16.414 13025.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,4) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_status_0\/main_4 7.126
macrocell3 U(1,1) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_4 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 4.188
statusicell1 U(1,1) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 61.463 MHz 16.270 13025.397
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 3.190
macrocell2 U(0,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.290
datapathcell2 U(0,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 63.633 MHz 15.715 13025.952
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:counter_load_not\/main_2 3.695
macrocell2 U(0,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.290
datapathcell2 U(0,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 64.181 MHz 15.581 13026.086
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,0) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 3.372
macrocell5 U(0,0) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.249
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 64.931 MHz 15.401 13026.266
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_3 3.783
macrocell3 U(1,1) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_3 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 4.188
statusicell1 U(1,1) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 65.283 MHz 15.318 13026.349
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,1) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_postpoll\/main_0 4.957
macrocell6 U(0,1) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.291
datapathcell3 U(0,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxSts\/status_0 65.604 MHz 15.243 13026.424
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_status_0\/main_0 5.955
macrocell3 U(1,1) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_0 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 4.188
statusicell1 U(1,1) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 7.188
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.445
macrocell15 U(0,0) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 7.188
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.445
macrocell24 U(0,0) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 7.194
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.451
macrocell18 U(0,0) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 7.194
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.451
macrocell23 U(0,0) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 7.922
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.179
macrocell21 U(0,1) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 7.922
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.179
macrocell22 U(0,1) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 13.672
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 6.288
macrocell6 U(0,1) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.291
datapathcell3 U(0,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 1.510
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(0,0) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.260
statusicell2 U(1,0) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 3.147
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 2.957
macrocell12 U(1,4) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_load_fifo\/main_6 3.191
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_load_fifo\/main_6 2.571
macrocell16 U(0,0) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_2\/main_6 3.191
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_2\/main_6 2.571
macrocell18 U(0,0) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_0\/main_6 3.202
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_0\/main_6 2.582
macrocell15 U(0,0) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_3\/main_6 3.202
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_3\/main_6 2.582
macrocell17 U(0,0) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 3.270
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 3.080
macrocell9 U(1,4) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 3.273
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 3.083
macrocell10 U(0,4) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_load_fifo\/main_7 3.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART_1:BUART:rx_count_4\ \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_load_fifo\/main_7 2.691
macrocell16 U(0,0) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_2\/main_7 3.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART_1:BUART:rx_count_4\ \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_2\/main_7 2.691
macrocell18 U(0,0) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\StatusReg:Sync:ctrl_reg\/control_1 Pin_2(0)_PAD 25.057
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,4) 1 \StatusReg:Sync:ctrl_reg\ \StatusReg:Sync:ctrl_reg\/busclk \StatusReg:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_25 \StatusReg:Sync:ctrl_reg\/control_1 Pin_2(0)/pin_input 7.205
iocell4 P0[1] 1 Pin_2(0) Pin_2(0)/pin_input Pin_2(0)/pad_out 15.802
Route 1 Pin_2(0)_PAD Pin_2(0)/pad_out Pin_2(0)_PAD 0.000
Clock Clock path delay 0.000
\StatusReg:Sync:ctrl_reg\/control_3 Pin_4(0)_PAD 24.750
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,4) 1 \StatusReg:Sync:ctrl_reg\ \StatusReg:Sync:ctrl_reg\/busclk \StatusReg:Sync:ctrl_reg\/control_3 2.050
Route 1 Net_27 \StatusReg:Sync:ctrl_reg\/control_3 Pin_4(0)/pin_input 6.956
iocell6 P0[3] 1 Pin_4(0) Pin_4(0)/pin_input Pin_4(0)/pad_out 15.744
Route 1 Pin_4(0)_PAD Pin_4(0)/pad_out Pin_4(0)_PAD 0.000
Clock Clock path delay 0.000
\StatusReg:Sync:ctrl_reg\/control_2 Pin_3(0)_PAD 24.537
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,4) 1 \StatusReg:Sync:ctrl_reg\ \StatusReg:Sync:ctrl_reg\/busclk \StatusReg:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_26 \StatusReg:Sync:ctrl_reg\/control_2 Pin_3(0)/pin_input 7.028
iocell5 P0[2] 1 Pin_3(0) Pin_3(0)/pin_input Pin_3(0)/pad_out 15.459
Route 1 Pin_3(0)_PAD Pin_3(0)/pad_out Pin_3(0)_PAD 0.000
Clock Clock path delay 0.000
\StatusReg:Sync:ctrl_reg\/control_0 Pin_1(0)_PAD 24.435
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,4) 1 \StatusReg:Sync:ctrl_reg\ \StatusReg:Sync:ctrl_reg\/busclk \StatusReg:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_24 \StatusReg:Sync:ctrl_reg\/control_0 Pin_1(0)/pin_input 7.134
iocell3 P0[0] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 15.251
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Reg:Sync:ctrl_reg\/control_0 Pin_6(0)_PAD 24.141
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,4) 1 \LED_Reg:Sync:ctrl_reg\ \LED_Reg:Sync:ctrl_reg\/busclk \LED_Reg:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_39 \LED_Reg:Sync:ctrl_reg\/control_0 Pin_6(0)/pin_input 6.424
iocell8 P2[0] 1 Pin_6(0) Pin_6(0)/pin_input Pin_6(0)/pad_out 15.667
Route 1 Pin_6(0)_PAD Pin_6(0)/pad_out Pin_6(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Reg:Sync:ctrl_reg\/control_5 Pin_11(0)_PAD 24.128
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,4) 1 \LED_Reg:Sync:ctrl_reg\ \LED_Reg:Sync:ctrl_reg\/busclk \LED_Reg:Sync:ctrl_reg\/control_5 2.050
Route 1 Net_44 \LED_Reg:Sync:ctrl_reg\/control_5 Pin_11(0)/pin_input 6.425
iocell13 P2[5] 1 Pin_11(0) Pin_11(0)/pin_input Pin_11(0)/pad_out 15.653
Route 1 Pin_11(0)_PAD Pin_11(0)/pad_out Pin_11(0)_PAD 0.000
Clock Clock path delay 0.000
\StatusReg:Sync:ctrl_reg\/control_4 Pin_5(0)_PAD 23.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,4) 1 \StatusReg:Sync:ctrl_reg\ \StatusReg:Sync:ctrl_reg\/busclk \StatusReg:Sync:ctrl_reg\/control_4 2.050
Route 1 Net_28 \StatusReg:Sync:ctrl_reg\/control_4 Pin_5(0)/pin_input 7.042
iocell7 P0[4] 1 Pin_5(0) Pin_5(0)/pin_input Pin_5(0)/pad_out 14.880
Route 1 Pin_5(0)_PAD Pin_5(0)/pad_out Pin_5(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Reg:Sync:ctrl_reg\/control_6 Pin_12(0)_PAD 23.635
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,4) 1 \LED_Reg:Sync:ctrl_reg\ \LED_Reg:Sync:ctrl_reg\/busclk \LED_Reg:Sync:ctrl_reg\/control_6 2.050
Route 1 Net_45 \LED_Reg:Sync:ctrl_reg\/control_6 Pin_12(0)/pin_input 6.461
iocell14 P2[6] 1 Pin_12(0) Pin_12(0)/pin_input Pin_12(0)/pad_out 15.124
Route 1 Pin_12(0)_PAD Pin_12(0)/pad_out Pin_12(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Reg:Sync:ctrl_reg\/control_1 Pin_7(0)_PAD 23.450
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,4) 1 \LED_Reg:Sync:ctrl_reg\ \LED_Reg:Sync:ctrl_reg\/busclk \LED_Reg:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_40 \LED_Reg:Sync:ctrl_reg\/control_1 Pin_7(0)/pin_input 5.509
iocell9 P2[1] 1 Pin_7(0) Pin_7(0)/pin_input Pin_7(0)/pad_out 15.891
Route 1 Pin_7(0)_PAD Pin_7(0)/pad_out Pin_7(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Reg:Sync:ctrl_reg\/control_2 Pin_8(0)_PAD 23.271
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,4) 1 \LED_Reg:Sync:ctrl_reg\ \LED_Reg:Sync:ctrl_reg\/busclk \LED_Reg:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_41 \LED_Reg:Sync:ctrl_reg\/control_2 Pin_8(0)/pin_input 5.434
iocell10 P2[2] 1 Pin_8(0) Pin_8(0)/pin_input Pin_8(0)/pad_out 15.787
Route 1 Pin_8(0)_PAD Pin_8(0)/pad_out Pin_8(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Reg:Sync:ctrl_reg\/control_3 Pin_9(0)_PAD 23.006
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,4) 1 \LED_Reg:Sync:ctrl_reg\ \LED_Reg:Sync:ctrl_reg\/busclk \LED_Reg:Sync:ctrl_reg\/control_3 2.050
Route 1 Net_42 \LED_Reg:Sync:ctrl_reg\/control_3 Pin_9(0)/pin_input 5.519
iocell11 P2[3] 1 Pin_9(0) Pin_9(0)/pin_input Pin_9(0)/pad_out 15.437
Route 1 Pin_9(0)_PAD Pin_9(0)/pad_out Pin_9(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Reg:Sync:ctrl_reg\/control_4 Pin_10(0)_PAD 22.813
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,4) 1 \LED_Reg:Sync:ctrl_reg\ \LED_Reg:Sync:ctrl_reg\/busclk \LED_Reg:Sync:ctrl_reg\/control_4 2.050
Route 1 Net_43 \LED_Reg:Sync:ctrl_reg\/control_4 Pin_10(0)/pin_input 5.414
iocell12 P2[4] 1 Pin_10(0) Pin_10(0)/pin_input Pin_10(0)/pad_out 15.349
Route 1 Pin_10(0)_PAD Pin_10(0)/pad_out Pin_10(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Reg:Sync:ctrl_reg\/control_7 Pin_13(0)_PAD 22.538
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,4) 1 \LED_Reg:Sync:ctrl_reg\ \LED_Reg:Sync:ctrl_reg\/busclk \LED_Reg:Sync:ctrl_reg\/control_7 2.050
Route 1 Net_46 \LED_Reg:Sync:ctrl_reg\/control_7 Pin_13(0)/pin_input 5.614
iocell15 P2[7] 1 Pin_13(0) Pin_13(0)/pin_input Pin_13(0)/pad_out 14.874
Route 1 Pin_13(0)_PAD Pin_13(0)/pad_out Pin_13(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 32.300
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_2/main_0 4.914
macrocell1 U(1,1) 1 Net_2 Net_2/main_0 Net_2/q 3.350
Route 1 Net_2 Net_2/q Tx_1(0)/pin_input 6.566
iocell2 P12[6] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.220
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000