\UART_1:BUART:tx_state_0\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
52.081 MHz |
19.201 |
13022.466 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell15 |
U(1,3) |
1 |
\UART_1:BUART:tx_state_0\ |
\UART_1:BUART:tx_state_0\/clock_0 |
\UART_1:BUART:tx_state_0\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_0\ |
\UART_1:BUART:tx_state_0\/q |
\UART_1:BUART:counter_load_not\/main_1 |
4.787 |
macrocell6 |
U(1,2) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_1 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
3.624 |
datapathcell3 |
U(1,0) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
53.787 MHz |
18.592 |
13023.075 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell3 |
U(1,0) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
0.190 |
Route |
|
1 |
\UART_1:BUART:tx_bitclk_enable_pre\ |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART_1:BUART:counter_load_not\/main_2 |
5.238 |
macrocell6 |
U(1,2) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_2 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
3.624 |
datapathcell3 |
U(1,0) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:rx_state_3\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
55.850 MHz |
17.905 |
13023.762 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell21 |
U(1,0) |
1 |
\UART_1:BUART:rx_state_3\ |
\UART_1:BUART:rx_state_3\/clock_0 |
\UART_1:BUART:rx_state_3\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:rx_state_3\ |
\UART_1:BUART:rx_state_3\/q |
\UART_1:BUART:rx_counter_load\/main_2 |
5.634 |
macrocell9 |
U(1,1) |
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/main_2 |
\UART_1:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
2.311 |
count7cell |
U(1,1) |
1 |
\UART_1:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_ctrl_mark_last\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
56.022 MHz |
17.850 |
13023.817 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell18 |
U(0,3) |
1 |
\UART_1:BUART:tx_ctrl_mark_last\ |
\UART_1:BUART:tx_ctrl_mark_last\/clock_0 |
\UART_1:BUART:tx_ctrl_mark_last\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_ctrl_mark_last\ |
\UART_1:BUART:tx_ctrl_mark_last\/q |
\UART_1:BUART:rx_counter_load\/main_0 |
5.579 |
macrocell9 |
U(1,1) |
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/main_0 |
\UART_1:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
2.311 |
count7cell |
U(1,1) |
1 |
\UART_1:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_state_1\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
57.169 MHz |
17.492 |
13024.175 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell14 |
U(0,2) |
1 |
\UART_1:BUART:tx_state_1\ |
\UART_1:BUART:tx_state_1\/clock_0 |
\UART_1:BUART:tx_state_1\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_1\ |
\UART_1:BUART:tx_state_1\/q |
\UART_1:BUART:counter_load_not\/main_0 |
3.078 |
macrocell6 |
U(1,2) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_0 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
3.624 |
datapathcell3 |
U(1,0) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_state_2\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
57.228 MHz |
17.474 |
13024.193 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell16 |
U(1,2) |
1 |
\UART_1:BUART:tx_state_2\ |
\UART_1:BUART:tx_state_2\/clock_0 |
\UART_1:BUART:tx_state_2\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_2\ |
\UART_1:BUART:tx_state_2\/q |
\UART_1:BUART:counter_load_not\/main_3 |
3.060 |
macrocell6 |
U(1,2) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_3 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
3.624 |
datapathcell3 |
U(1,0) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:rx_state_0\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
59.042 MHz |
16.937 |
13024.730 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell19 |
U(0,0) |
1 |
\UART_1:BUART:rx_state_0\ |
\UART_1:BUART:rx_state_0\/clock_0 |
\UART_1:BUART:rx_state_0\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:rx_state_0\ |
\UART_1:BUART:rx_state_0\/q |
\UART_1:BUART:rx_counter_load\/main_1 |
4.666 |
macrocell9 |
U(1,1) |
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/main_1 |
\UART_1:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
2.311 |
count7cell |
U(1,1) |
1 |
\UART_1:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:rx_state_2\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
59.063 MHz |
16.931 |
13024.736 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell22 |
U(1,0) |
1 |
\UART_1:BUART:rx_state_2\ |
\UART_1:BUART:rx_state_2\/clock_0 |
\UART_1:BUART:rx_state_2\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:rx_state_2\ |
\UART_1:BUART:rx_state_2\/q |
\UART_1:BUART:rx_counter_load\/main_3 |
4.660 |
macrocell9 |
U(1,1) |
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/main_3 |
\UART_1:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
2.311 |
count7cell |
U(1,1) |
1 |
\UART_1:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb |
\UART_1:BUART:sRX:RxSts\/status_4 |
65.569 MHz |
15.251 |
13026.416 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell4 |
U(0,1) |
1 |
\UART_1:BUART:sRX:RxShifter:u0\ |
\UART_1:BUART:sRX:RxShifter:u0\/clock |
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb |
3.580 |
Route |
|
1 |
\UART_1:BUART:rx_fifofull\ |
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb |
\UART_1:BUART:rx_status_4\/main_1 |
2.306 |
macrocell11 |
U(0,1) |
1 |
\UART_1:BUART:rx_status_4\ |
\UART_1:BUART:rx_status_4\/main_1 |
\UART_1:BUART:rx_status_4\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_status_4\ |
\UART_1:BUART:rx_status_4\/q |
\UART_1:BUART:sRX:RxSts\/status_4 |
5.515 |
statusicell3 |
U(0,1) |
1 |
\UART_1:BUART:sRX:RxSts\ |
|
SETUP |
0.500 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:pollcount_1\/q |
\UART_1:BUART:sRX:RxShifter:u0\/route_si |
67.331 MHz |
14.852 |
13026.815 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell25 |
U(0,2) |
1 |
\UART_1:BUART:pollcount_1\ |
\UART_1:BUART:pollcount_1\/clock_0 |
\UART_1:BUART:pollcount_1\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:pollcount_1\ |
\UART_1:BUART:pollcount_1\/q |
\UART_1:BUART:rx_postpoll\/main_0 |
4.491 |
macrocell10 |
U(0,1) |
1 |
\UART_1:BUART:rx_postpoll\ |
\UART_1:BUART:rx_postpoll\/main_0 |
\UART_1:BUART:rx_postpoll\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_postpoll\ |
\UART_1:BUART:rx_postpoll\/q |
\UART_1:BUART:sRX:RxShifter:u0\/route_si |
2.291 |
datapathcell4 |
U(0,1) |
1 |
\UART_1:BUART:sRX:RxShifter:u0\ |
|
SETUP |
3.470 |
Clock |
|
|
|
|
Skew |
0.000 |
|