Static Timing Analysis

Project : PSoC LED Sign 1
Build Time : 08/07/18 10:44:56
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 59.035 MHz
UART_1_IntClock CyMASTER_CLK 76.677 kHz 76.677 kHz 52.081 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ShiftReg_1:bSR:SyncCtl:CtrlReg\/control_0 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/cs_addr_2 104.998 MHz 9.524 32.143
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,2) 1 \ShiftReg_1:bSR:SyncCtl:CtrlReg\ \ShiftReg_1:bSR:SyncCtl:CtrlReg\/clock \ShiftReg_1:bSR:SyncCtl:CtrlReg\/control_0 1.210
Route 1 \ShiftReg_1:bSR:ctrl_clk_enable\ \ShiftReg_1:bSR:SyncCtl:CtrlReg\/control_0 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/cs_addr_2 2.304
datapathcell1 U(0,2) 1 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\ SETUP 6.010
Clock Skew 0.000
\ClockReg:Sync:ctrl_reg\/control_0 \ShiftReg_1:bSR:StsReg\/clk_en 119.446 MHz 8.372 33.295
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \ClockReg:Sync:ctrl_reg\ \ClockReg:Sync:ctrl_reg\/busclk \ClockReg:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_122 \ClockReg:Sync:ctrl_reg\/control_0 \ShiftReg_1:bSR:StsReg\/clk_en 4.222
statusicell1 U(0,2) 1 \ShiftReg_1:bSR:StsReg\ SETUP 2.100
Clock Skew 0.000
\ClockReg:Sync:ctrl_reg\/control_0 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/clk_en 119.446 MHz 8.372 33.295
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \ClockReg:Sync:ctrl_reg\ \ClockReg:Sync:ctrl_reg\/busclk \ClockReg:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_122 \ClockReg:Sync:ctrl_reg\/control_0 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/clk_en 4.222
datapathcell1 U(0,2) 1 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\ SETUP 2.100
Clock Skew 0.000
\ClockReg:Sync:ctrl_reg\/control_0 \ShiftReg_1:bSR:SyncCtl:CtrlReg\/clk_en 124.363 MHz 8.041 33.626
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \ClockReg:Sync:ctrl_reg\ \ClockReg:Sync:ctrl_reg\/busclk \ClockReg:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_122 \ClockReg:Sync:ctrl_reg\/control_0 \ShiftReg_1:bSR:SyncCtl:CtrlReg\/clk_en 3.891
controlcell3 U(1,2) 1 \ShiftReg_1:bSR:SyncCtl:CtrlReg\ SETUP 2.100
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 59.035 MHz 16.939 24.728
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_98 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.819
macrocell10 U(0,1) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.291
datapathcell4 U(0,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 79.700 MHz 12.547 29.120
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_98 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 7.028
macrocell25 U(0,2) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 85.962 MHz 11.633 30.034
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_98 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.114
macrocell26 U(0,1) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 92.713 MHz 10.786 30.881
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_98 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.267
macrocell22 U(1,0) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 92.713 MHz 10.786 30.881
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_98 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.267
macrocell28 U(1,0) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 92.790 MHz 10.777 30.890
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_98 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.258
macrocell19 U(0,0) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 92.790 MHz 10.777 30.890
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_98 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.258
macrocell27 U(0,0) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 52.081 MHz 19.201 13022.466
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,3) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 4.787
macrocell6 U(1,2) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.624
datapathcell3 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 53.787 MHz 18.592 13023.075
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:counter_load_not\/main_2 5.238
macrocell6 U(1,2) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.624
datapathcell3 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:sRX:RxBitCounter\/load 55.850 MHz 17.905 13023.762
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,0) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_counter_load\/main_2 5.634
macrocell9 U(1,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_2 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.311
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:sRX:RxBitCounter\/load 56.022 MHz 17.850 13023.817
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,3) 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/clock_0 \UART_1:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_counter_load\/main_0 5.579
macrocell9 U(1,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.311
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 57.169 MHz 17.492 13024.175
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,2) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 3.078
macrocell6 U(1,2) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.624
datapathcell3 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 57.228 MHz 17.474 13024.193
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(1,2) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 3.060
macrocell6 U(1,2) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.624
datapathcell3 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 59.042 MHz 16.937 13024.730
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,0) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 4.666
macrocell9 U(1,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.311
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 59.063 MHz 16.931 13024.736
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,0) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 4.660
macrocell9 U(1,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.311
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sRX:RxSts\/status_4 65.569 MHz 15.251 13026.416
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ \UART_1:BUART:sRX:RxShifter:u0\/clock \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_1:BUART:rx_fifofull\ \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:rx_status_4\/main_1 2.306
macrocell11 U(0,1) 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/main_1 \UART_1:BUART:rx_status_4\/q 3.350
Route 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/q \UART_1:BUART:sRX:RxSts\/status_4 5.515
statusicell3 U(0,1) 1 \UART_1:BUART:sRX:RxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 67.331 MHz 14.852 13026.815
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,2) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_postpoll\/main_0 4.491
macrocell10 U(0,1) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.291
datapathcell4 U(0,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\ShiftReg_1:bSR:SyncCtl:CtrlReg\/control_0 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/cs_addr_2 2.664
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,2) 1 \ShiftReg_1:bSR:SyncCtl:CtrlReg\ \ShiftReg_1:bSR:SyncCtl:CtrlReg\/clock \ShiftReg_1:bSR:SyncCtl:CtrlReg\/control_0 0.360
Route 1 \ShiftReg_1:bSR:ctrl_clk_enable\ \ShiftReg_1:bSR:SyncCtl:CtrlReg\/control_0 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/cs_addr_2 2.304
datapathcell1 U(0,2) 1 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\ HOLD 0.000
Clock Skew 0.000
\ClockReg:Sync:ctrl_reg\/control_0 \ShiftReg_1:bSR:SyncCtl:CtrlReg\/clk_en 4.511
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \ClockReg:Sync:ctrl_reg\ \ClockReg:Sync:ctrl_reg\/busclk \ClockReg:Sync:ctrl_reg\/control_0 0.620
Route 1 Net_122 \ClockReg:Sync:ctrl_reg\/control_0 \ShiftReg_1:bSR:SyncCtl:CtrlReg\/clk_en 3.891
controlcell3 U(1,2) 1 \ShiftReg_1:bSR:SyncCtl:CtrlReg\ HOLD 0.000
Clock Skew 0.000
\ClockReg:Sync:ctrl_reg\/control_0 \ShiftReg_1:bSR:StsReg\/clk_en 4.842
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \ClockReg:Sync:ctrl_reg\ \ClockReg:Sync:ctrl_reg\/busclk \ClockReg:Sync:ctrl_reg\/control_0 0.620
Route 1 Net_122 \ClockReg:Sync:ctrl_reg\/control_0 \ShiftReg_1:bSR:StsReg\/clk_en 4.222
statusicell1 U(0,2) 1 \ShiftReg_1:bSR:StsReg\ HOLD 0.000
Clock Skew 0.000
\ClockReg:Sync:ctrl_reg\/control_0 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/clk_en 4.842
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \ClockReg:Sync:ctrl_reg\ \ClockReg:Sync:ctrl_reg\/busclk \ClockReg:Sync:ctrl_reg\/control_0 0.620
Route 1 Net_122 \ClockReg:Sync:ctrl_reg\/control_0 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/clk_en 4.222
datapathcell1 U(0,2) 1 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 7.267
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_98 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.258
macrocell19 U(0,0) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 7.267
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_98 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.258
macrocell27 U(0,0) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 7.276
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_98 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.267
macrocell22 U(1,0) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 7.276
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_98 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.267
macrocell28 U(1,0) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 8.123
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_98 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.114
macrocell26 U(0,1) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 9.037
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_98 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 7.028
macrocell25 U(0,2) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 13.469
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_98 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.819
macrocell10 U(0,1) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.291
datapathcell4 U(0,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.118
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(0,0) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.868
statusicell3 U(0,1) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_0 \UART_1:BUART:rx_bitclk_enable\/main_2 2.925
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART_1:BUART:rx_count_0\ \UART_1:BUART:sRX:RxBitCounter\/count_0 \UART_1:BUART:rx_bitclk_enable\/main_2 2.305
macrocell23 U(1,1) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:rx_bitclk_enable\/main_1 3.229
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:rx_bitclk_enable\/main_1 2.609
macrocell23 U(1,1) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:pollcount_0\/main_1 3.229
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:pollcount_0\/main_1 2.609
macrocell26 U(0,1) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_last\/q \UART_1:BUART:rx_state_2\/main_9 3.495
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(1,0) 1 \UART_1:BUART:rx_last\ \UART_1:BUART:rx_last\/clock_0 \UART_1:BUART:rx_last\/q 1.250
Route 1 \UART_1:BUART:rx_last\ \UART_1:BUART:rx_last\/q \UART_1:BUART:rx_state_2\/main_9 2.245
macrocell22 U(1,0) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:pollcount_0\/main_0 3.578
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_1:BUART:rx_count_2\ \UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:pollcount_0\/main_0 2.958
macrocell26 U(0,1) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:rx_bitclk_enable\/main_0 3.579
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_1:BUART:rx_count_2\ \UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:rx_bitclk_enable\/main_0 2.959
macrocell23 U(1,1) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 3.804
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,3) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/so_comb 1.510
Route 1 \UART_1:BUART:tx_shift_out\ \UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 2.294
macrocell13 U(0,3) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:pollcount_1\/main_2 3.871
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,2) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
macrocell25 U(0,2) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:pollcount_1\/main_2 2.621
macrocell25 U(0,2) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:tx_state_0\/main_5 4.012
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,3) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:tx_state_0\/main_5 2.762
macrocell15 U(1,3) 1 \UART_1:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/so_comb Shift_Data_Upper(0)_PAD 33.333
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,2) 1 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\ \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/clock \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/so_comb 5.160
Route 1 Net_163 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/so_comb Net_10/main_1 2.809
macrocell1 U(0,2) 1 Net_10 Net_10/main_1 Net_10/q 3.350
Route 1 Net_10 Net_10/q Shift_Data_Upper(0)/pin_input 6.633
iocell1 P1[7] 1 Shift_Data_Upper(0) Shift_Data_Upper(0)/pin_input Shift_Data_Upper(0)/pad_out 15.381
Route 1 Shift_Data_Upper(0)_PAD Shift_Data_Upper(0)/pad_out Shift_Data_Upper(0)_PAD 0.000
Clock Clock path delay 0.000
\ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/so_comb Shift_Data_Lower(0)_PAD 32.447
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,2) 1 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\ \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/clock \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/so_comb 5.160
Route 1 Net_163 \ShiftReg_1:bSR:sC8:BShiftRegDp:u0\/so_comb Net_11/main_1 2.775
macrocell2 U(0,2) 1 Net_11 Net_11/main_1 Net_11/q 3.350
Route 1 Net_11 Net_11/q Shift_Data_Lower(0)/pin_input 5.820
iocell2 P1[5] 1 Shift_Data_Lower(0) Shift_Data_Lower(0)/pin_input Shift_Data_Lower(0)/pad_out 15.342
Route 1 Shift_Data_Lower(0)_PAD Shift_Data_Lower(0)/pad_out Shift_Data_Lower(0)_PAD 0.000
Clock Clock path delay 0.000
\RowControl:Sync:ctrl_reg\/control_0 Clock_Lower(0)_PAD 30.433
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \RowControl:Sync:ctrl_reg\ \RowControl:Sync:ctrl_reg\/busclk \RowControl:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_121 \RowControl:Sync:ctrl_reg\/control_0 Net_13/main_0 3.914
macrocell4 U(0,1) 1 Net_13 Net_13/main_0 Net_13/q 3.350
Route 1 Net_13 Net_13/q Clock_Lower(0)/pin_input 5.441
iocell4 P1[4] 1 Clock_Lower(0) Clock_Lower(0)/pin_input Clock_Lower(0)/pad_out 15.678
Route 1 Clock_Lower(0)_PAD Clock_Lower(0)/pad_out Clock_Lower(0)_PAD 0.000
Clock Clock path delay 0.000
\ClockReg:Sync:ctrl_reg\/control_0 Clock_Upper(0)_PAD 30.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \ClockReg:Sync:ctrl_reg\ \ClockReg:Sync:ctrl_reg\/busclk \ClockReg:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_122 \ClockReg:Sync:ctrl_reg\/control_0 Net_12/main_1 4.184
macrocell3 U(0,2) 1 Net_12 Net_12/main_1 Net_12/q 3.350
Route 1 Net_12 Net_12/q Clock_Upper(0)/pin_input 5.580
iocell3 P1[6] 1 Clock_Upper(0) Clock_Upper(0)/pin_input Clock_Upper(0)/pad_out 15.071
Route 1 Clock_Upper(0)_PAD Clock_Upper(0)/pad_out Clock_Upper(0)_PAD 0.000
Clock Clock path delay 0.000
\G_Bar:Sync:ctrl_reg\/control_0 G_Bar_Out(0)_PAD 24.712
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(1,3) 1 \G_Bar:Sync:ctrl_reg\ \G_Bar:Sync:ctrl_reg\/busclk \G_Bar:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_139 \G_Bar:Sync:ctrl_reg\/control_0 G_Bar_Out(0)/pin_input 6.996
iocell8 P12[2] 1 G_Bar_Out(0) G_Bar_Out(0)/pin_input G_Bar_Out(0)/pad_out 15.666
Route 1 G_Bar_Out(0)_PAD G_Bar_Out(0)/pad_out G_Bar_Out(0)_PAD 0.000
Clock Clock path delay 0.000
\FET_Ctrl:Sync:ctrl_reg\/control_5 FET_5(0)_PAD 24.290
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,3) 1 \FET_Ctrl:Sync:ctrl_reg\ \FET_Ctrl:Sync:ctrl_reg\/busclk \FET_Ctrl:Sync:ctrl_reg\/control_5 2.050
Route 1 Net_155 \FET_Ctrl:Sync:ctrl_reg\/control_5 FET_5(0)/pin_input 6.587
iocell14 P2[5] 1 FET_5(0) FET_5(0)/pin_input FET_5(0)/pad_out 15.653
Route 1 FET_5(0)_PAD FET_5(0)/pad_out FET_5(0)_PAD 0.000
Clock Clock path delay 0.000
\FET_Ctrl:Sync:ctrl_reg\/control_6 FET_6(0)_PAD 23.766
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,3) 1 \FET_Ctrl:Sync:ctrl_reg\ \FET_Ctrl:Sync:ctrl_reg\/busclk \FET_Ctrl:Sync:ctrl_reg\/control_6 2.050
Route 1 Net_156 \FET_Ctrl:Sync:ctrl_reg\/control_6 FET_6(0)/pin_input 6.592
iocell15 P2[6] 1 FET_6(0) FET_6(0)/pin_input FET_6(0)/pad_out 15.124
Route 1 FET_6(0)_PAD FET_6(0)/pad_out FET_6(0)_PAD 0.000
Clock Clock path delay 0.000
\FET_Ctrl:Sync:ctrl_reg\/control_1 FET_1(0)_PAD 23.722
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,3) 1 \FET_Ctrl:Sync:ctrl_reg\ \FET_Ctrl:Sync:ctrl_reg\/busclk \FET_Ctrl:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_151 \FET_Ctrl:Sync:ctrl_reg\/control_1 FET_1(0)/pin_input 5.781
iocell10 P2[1] 1 FET_1(0) FET_1(0)/pin_input FET_1(0)/pad_out 15.891
Route 1 FET_1(0)_PAD FET_1(0)/pad_out FET_1(0)_PAD 0.000
Clock Clock path delay 0.000
\FET_Ctrl:Sync:ctrl_reg\/control_2 FET_2(0)_PAD 23.696
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,3) 1 \FET_Ctrl:Sync:ctrl_reg\ \FET_Ctrl:Sync:ctrl_reg\/busclk \FET_Ctrl:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_152 \FET_Ctrl:Sync:ctrl_reg\/control_2 FET_2(0)/pin_input 5.859
iocell11 P2[2] 1 FET_2(0) FET_2(0)/pin_input FET_2(0)/pad_out 15.787
Route 1 FET_2(0)_PAD FET_2(0)/pad_out FET_2(0)_PAD 0.000
Clock Clock path delay 0.000
\FET_Ctrl:Sync:ctrl_reg\/control_0 FET_0(0)_PAD 23.661
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,3) 1 \FET_Ctrl:Sync:ctrl_reg\ \FET_Ctrl:Sync:ctrl_reg\/busclk \FET_Ctrl:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_150 \FET_Ctrl:Sync:ctrl_reg\/control_0 FET_0(0)/pin_input 5.944
iocell9 P2[0] 1 FET_0(0) FET_0(0)/pin_input FET_0(0)/pad_out 15.667
Route 1 FET_0(0)_PAD FET_0(0)/pad_out FET_0(0)_PAD 0.000
Clock Clock path delay 0.000
\FET_Ctrl:Sync:ctrl_reg\/control_3 FET_3(0)_PAD 23.260
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,3) 1 \FET_Ctrl:Sync:ctrl_reg\ \FET_Ctrl:Sync:ctrl_reg\/busclk \FET_Ctrl:Sync:ctrl_reg\/control_3 2.050
Route 1 Net_153 \FET_Ctrl:Sync:ctrl_reg\/control_3 FET_3(0)/pin_input 5.773
iocell12 P2[3] 1 FET_3(0) FET_3(0)/pin_input FET_3(0)/pad_out 15.437
Route 1 FET_3(0)_PAD FET_3(0)/pad_out FET_3(0)_PAD 0.000
Clock Clock path delay 0.000
\RCK:Sync:ctrl_reg\/control_0 RCK_Out(0)_PAD 23.234
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,0) 1 \RCK:Sync:ctrl_reg\ \RCK:Sync:ctrl_reg\/busclk \RCK:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_106 \RCK:Sync:ctrl_reg\/control_0 RCK_Out(0)/pin_input 5.714
iocell7 P1[2] 1 RCK_Out(0) RCK_Out(0)/pin_input RCK_Out(0)/pad_out 15.470
Route 1 RCK_Out(0)_PAD RCK_Out(0)/pad_out RCK_Out(0)_PAD 0.000
Clock Clock path delay 0.000
\FET_Ctrl:Sync:ctrl_reg\/control_4 FET_4(0)_PAD 23.194
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,3) 1 \FET_Ctrl:Sync:ctrl_reg\ \FET_Ctrl:Sync:ctrl_reg\/busclk \FET_Ctrl:Sync:ctrl_reg\/control_4 2.050
Route 1 Net_154 \FET_Ctrl:Sync:ctrl_reg\/control_4 FET_4(0)/pin_input 5.795
iocell13 P2[4] 1 FET_4(0) FET_4(0)/pin_input FET_4(0)/pad_out 15.349
Route 1 FET_4(0)_PAD FET_4(0)/pad_out FET_4(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 31.128
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(0,3) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_93/main_0 2.797
macrocell5 U(0,3) 1 Net_93 Net_93/main_0 Net_93/q 3.350
Route 1 Net_93 Net_93/q Tx_1(0)/pin_input 6.764
iocell6 P12[7] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.967
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000