********** Mapped Logic ********** |
!Q0.T := Gnd; // (0 pt, 0 inp)
Q0.CLK = clk; // GCK (0 pt, 0 inp) |
Q1.T := !Q0; // (1 pt, 1 inp)
Q1.CLK = clk; // GCK (0 pt, 0 inp) |
Q2.T := !Q0 & !Q1; // (1 pt, 2 inp)
Q2.CLK = clk; // GCK (0 pt, 0 inp) |
Q3.T := !Q0 & !Q1 & !Q2; // (1 pt, 3 inp)
Q3.CLK = clk; // GCK (0 pt, 0 inp) |
Control Term Legend:
Clock - GCK - Global Clock CTC - Block Control Term Clock PTC - Product Term Clock CLKDIV - Clock Divider Preset - GSR - Global Set CTS - Block Control Term Preset PTA - Product Term Preset Reset - GSR - Global Reset CTR - Block Control Term Reset PTA - Product Term Reset Output Enable - GTS - Global Tristate CTE - Block Control Term Output Enable PTB - Product Term Output Enable |
Legend: as the FastInput "signal" (not logically related) |