Timing Report

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Design Name and_gate
Device, Speed (SpeedFile Version) XC2C64A, -5 (14.0 Advance Product Specification)
Date Created Fri Mar 07 18:03:43 2008
Created By Timing Report Generator: version J.40
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Pad to Pad Delay (tPD) 6.300 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
AUTO_TS_F2F 0.0 0.0 0 0
AUTO_TS_P2P 0.0 6.3 2 2
AUTO_TS_P2F 0.0 0.0 0 0
AUTO_TS_F2P 0.0 0.0 0 0


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
inputA to outputC 0.000 6.300 -6.300
inputB to outputC 0.000 6.300 -6.300


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)



Number of constraints not met: 1

Data Sheet Report

Pad to Pad List

Source Pad Destination Pad Delay
inputA outputC 6.300
inputB outputC 6.300



Number of paths analyzed: 2
Number of Timing errors: 2
Analysis Completed: Fri Mar 07 18:03:43 2008