cpldfit:  version J.40                              Xilinx Inc.
                                  Fitter Report
Design Name: ledinver                            Date:  3- 9-2008,  3:06PM
Device Used: XC2C64A-5-VQ44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
4  /64  (  6%) 3   /224  (  1%) 3   /160  (  2%) 4  /64  (  6%) 5  /33  ( 15%)

** Function Block Resources **

Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1       4/16      3/40     3/56     4/ 8    0/1      0/1      0/1      0/1
FB2       0/16      0/40     0/56     0/ 9    0/1      0/1      0/1      0/1
FB3       0/16      0/40     0/56     0/ 9    0/1      0/1      0/1      0/1
FB4       0/16      0/40     0/56     0/ 7    0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total     4/64      3/160    3/224    4/33    0/4      0/4      0/4      0/4 

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** Global Control Resources **

GCK         GSR         GTS         
Used/Tot    Used/Tot    Used/Tot    
1/3         0/1         0/4

Signal 'clk' mapped onto global clock net GCK0.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    0           0    |  I/O              :     3     25
Output        :    4           4    |  GCK/IO           :     1      3
Bidirectional :    0           0    |  GTS/IO           :     1      4
GCK           :    1           1    |  GSR/IO           :     0      1
GTS           :    0           0    |  
GSR           :    0           0    |  
                 ----        ----
        Total      5           5

End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 4 Outputs **

Signal              Total Total Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                Pts   Inps          No.   Type      Use     STD      Style     Rate Use     State
Q3                  1     3     FB1_1   38    I/O       O       LVCMOS18           FAST TFF/S   SET
Q2                  1     2     FB1_2   37    I/O       O       LVCMOS18           FAST TFF/S   SET
Q1                  1     1     FB1_3   36    I/O       O       LVCMOS18           FAST TFF/S   SET
Q0                  0     0     FB1_9   34    GTS/I/O   O       LVCMOS18           FAST TFF/S   SET

** 1 Inputs **

Signal              Loc     Pin   Pin       Pin     I/O      I/O
Name                        No.   Type      Use     STD      Style
clk                 FB2_7   43    GCK/I/O   GCK     LVCMOS18 KPR

Legend:
Pin No.   - ~     - User Assigned
I/O Style - OD    - OpenDrain
          - PU    - Pullup
          - KPR   - Keeper
          - S     - SchmittTrigger
          - DG    - DataGate
Reg Use   - LATCH - Transparent latch
          - DFF   - D-flip-flop
          - DEFF  - D-flip-flop with clock enable
          - TFF   - T-flip-flop
          - TDFF  - Dual-edge-triggered T-flip-flop
          - DDFF  - Dual-edge-triggered flip-flop
          - DDEFF - Dual-edge-triggered flip-flop with clock enable
          /S (after any above flop/latch type) indicates initial state is Set
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
              VRF - Vref
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               3/37
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   3/53
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Q3                            1     FB1_1   38   I/O     O                 
Q2                            1     FB1_2   37   I/O     O                 
Q1                            1     FB1_3   36   I/O     O                 
(unused)                      0     FB1_4        (b)           
(unused)                      0     FB1_5        (b)           
(unused)                      0     FB1_6        (b)           
(unused)                      0     FB1_7        (b)           
(unused)                      0     FB1_8        (b)           
Q0                            0     FB1_9   34   GTS/I/O O                 
(unused)                      0     FB1_10  33   GTS/I/O       
(unused)                      0     FB1_11  32   GTS/I/O       
(unused)                      0     FB1_12  31   GTS/I/O       
(unused)                      0     FB1_13  30   GSR/I/O       
(unused)                      0     FB1_14       (b)           
(unused)                      0     FB1_15       (b)           
(unused)                      0     FB1_16       (b)           

Signals Used by Logic in Function Block
  1: Q0                 2: Q1                 3: Q2 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Q3                XXX..................................... 3       
Q2                XX...................................... 2       
Q1                X....................................... 1       
Q0                ........................................ 0       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB2_1   39   I/O           
(unused)                      0     FB2_2   40   I/O           
(unused)                      0     FB2_3        (b)           
(unused)                      0     FB2_4        (b)           
(unused)                      0     FB2_5   41   I/O           
(unused)                      0     FB2_6   42   I/O           
(unused)                      0     FB2_7   43   GCK/I/O GCK   
(unused)                      0     FB2_8   44   GCK/I/O       
(unused)                      0     FB2_9        (b)           
(unused)                      0     FB2_10  1    GCK/I/O       
(unused)                      0     FB2_11       (b)           
(unused)                      0     FB2_12  2    I/O           
(unused)                      0     FB2_13  3    I/O           
(unused)                      0     FB2_14       (b)           
(unused)                      0     FB2_15       (b)           
(unused)                      0     FB2_16       (b)           
*********************************** FB3  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB3_1   29   I/O           
(unused)                      0     FB3_2   28   I/O           
(unused)                      0     FB3_3   27   I/O           
(unused)                      0     FB3_4        (b)           
(unused)                      0     FB3_5        (b)           
(unused)                      0     FB3_6   23   I/O           
(unused)                      0     FB3_7        (b)           
(unused)                      0     FB3_8        (b)           
(unused)                      0     FB3_9        (b)           
(unused)                      0     FB3_10  22   I/O           
(unused)                      0     FB3_11  21   I/O           
(unused)                      0     FB3_12  20   I/O           
(unused)                      0     FB3_13       (b)           
(unused)                      0     FB3_14  19   I/O           
(unused)                      0     FB3_15  18   I/O           
(unused)                      0     FB3_16       (b)           
*********************************** FB4  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB4_1   5    I/O           
(unused)                      0     FB4_2   6    I/O           
(unused)                      0     FB4_3        (b)           
(unused)                      0     FB4_4        (b)           
(unused)                      0     FB4_5        (b)           
(unused)                      0     FB4_6        (b)           
(unused)                      0     FB4_7   8    I/O           
(unused)                      0     FB4_8        (b)           
(unused)                      0     FB4_9        (b)           
(unused)                      0     FB4_10       (b)           
(unused)                      0     FB4_11  12   I/O           
(unused)                      0     FB4_12       (b)           
(unused)                      0     FB4_13  13   I/O           
(unused)                      0     FB4_14  14   I/O           
(unused)                      0     FB4_15  16   I/O           
(unused)                      0     FB4_16       (b)           
*******************************  Equations  ********************************

********** Mapped Logic **********

!Q0.T := Gnd;	// (0 pt, 0 inp)
   Q0.CLK  =  clk;	// GCK	(0 pt, 0 inp)

Q1.T := !Q0;	// (1 pt, 1 inp)
   Q1.CLK  =  clk;	// GCK	(0 pt, 0 inp)

Q2.T := !Q0 & !Q1;	// (1 pt, 2 inp)
   Q2.CLK  =  clk;	// GCK	(0 pt, 0 inp)

Q3.T := !Q0 & !Q1 & !Q2;	// (1 pt, 3 inp)
   Q3.CLK  =  clk;	// GCK	(0 pt, 0 inp)

Control Term Legend:
Clock         - GCK    - Global Clock
                CTC    - Block Control Term Clock
                PTC    - Product Term Clock
                CLKDIV - Clock Divider
Preset        - GSR    - Global Set
                CTS    - Block Control Term Preset
                PTA    - Product Term Preset
Reset         - GSR    - Global Reset
                CTR    - Block Control Term Reset
                PTA    - Product Term Reset
Output Enable - GTS    - Global Tristate
                CTE    - Block Control Term Output Enable
                PTB    - Product Term Output Enable

Legend:  .COMB = combinational node mapped to the same physical macrocell
                          as the FastInput "signal" (not logically related)
******************************  Device Pin Out *****************************

Device : XC2C64A-5-VQ44


   --------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 \
 | 1                             33 | 
 | 2                             32 | 
 | 3                             31 | 
 | 4                             30 | 
 | 5         XC2C64A-5-VQ44      29 | 
 | 6                             28 | 
 | 7                             27 | 
 | 8                             26 | 
 | 9                             25 | 
 | 10                            24 | 
 | 11                            23 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 KPR                              23 KPR                           
  2 KPR                              24 TDO                           
  3 KPR                              25 GND                           
  4 GND                              26 VCCIO-1.8                     
  5 KPR                              27 KPR                           
  6 KPR                              28 KPR                           
  7 VCCIO-1.8                        29 KPR                           
  8 KPR                              30 KPR                           
  9 TDI                              31 KPR                           
 10 TMS                              32 KPR                           
 11 TCK                              33 KPR                           
 12 KPR                              34 Q0                            
 13 KPR                              35 VCCAUX                        
 14 KPR                              36 Q1                            
 15 VCC                              37 Q2                            
 16 KPR                              38 Q3                            
 17 GND                              39 KPR                           
 18 KPR                              40 KPR                           
 19 KPR                              41 KPR                           
 20 KPR                              42 KPR                           
 21 KPR                              43 clk                           
 22 KPR                              44 KPR                           


Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc2c64a-5-VQ44
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : KEEPER
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28