Design Name | ledinver |
Fitting Status | Successful |
Software Version | J.40 |
Device Used | XC2C64A-5-VQ44 |
Date | 3- 9-2008, 3:06PM |
Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
---|---|---|---|---|
4/64 (7%) | 3/224 (2%) | 4/64 (7%) | 5/33 (16%) | 3/160 (2%) |
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Signal mapped onto global clock net (GCK0) | clk |