Design Name | and_gate |
Device, Speed (SpeedFile Version) | XC2C64A, -5 (14.0 Advance Product Specification) |
Date Created | Fri Mar 07 18:03:43 2008 |
Created By | Timing Report Generator: version J.40 |
Copyright | Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
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Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Performance Summary | |
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Pad to Pad Delay (tPD) | 6.300 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
AUTO_TS_F2F | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_P2P | 0.0 | 6.3 | 2 | 2 |
AUTO_TS_P2F | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2P | 0.0 | 0.0 | 0 | 0 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
inputA to outputC | 0.000 | 6.300 | -6.300 |
inputB to outputC | 0.000 | 6.300 | -6.300 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Source Pad | Destination Pad | Delay |
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inputA | outputC | 6.300 |
inputB | outputC | 6.300 |