Timing Report

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Design Name ledinver
Device, Speed (SpeedFile Version) XC2C64A, -5 (14.0 Advance Product Specification)
Date Created Sun Mar 09 15:06:55 2008
Created By Timing Report Generator: version J.40
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 3.800 ns.
Max. Clock Frequency (fSYSTEM) 263.158 MHz.
Limited by Cycle Time for clk
Clock to Setup (tCYC) 3.800 ns.
Clock Pad to Output Pad Delay (tCO) 3.900 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 3.8 6 6
AUTO_TS_P2P 0.0 3.9 4 4
AUTO_TS_P2F 0.0 1.6 1 1
AUTO_TS_F2P 0.0 2.3 4 4


Constraint: TS1000

Description: PERIOD:PERIOD_clk:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Q0.Q to Q1.D 0.000 3.800 -3.800
Q0.Q to Q2.D 0.000 3.800 -3.800
Q0.Q to Q3.D 0.000 3.800 -3.800


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
clk to Q0 0.000 3.900 -3.900
clk to Q1 0.000 3.900 -3.900
clk to Q2 0.000 3.900 -3.900
clk to Q3 0.000 3.900 -3.900


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
clk to clk.GCK 0.000 1.600 -1.600


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Q0.Q to Q0 0.000 2.300 -2.300
Q1.Q to Q1 0.000 2.300 -2.300
Q2.Q to Q2 0.000 2.300 -2.300
Q3.Q to Q3 0.000 2.300 -2.300



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
clk 263.158 Limited by Cycle Time for clk

Setup/Hold Times for Clocks


Clock to Pad Timing

Clock clk to Pad
Destination Pad Clock (edge) to Pad
Q0 3.900
Q1 3.900
Q2 3.900
Q3 3.900


Clock to Setup Times for Clocks

Clock to Setup for clock clk
Source Destination Delay
Q0.Q Q1.D 3.800
Q0.Q Q2.D 3.800
Q0.Q Q3.D 3.800
Q1.Q Q2.D 3.800
Q1.Q Q3.D 3.800
Q2.Q Q3.D 3.800


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 15
Number of Timing errors: 15
Analysis Completed: Sun Mar 09 15:06:55 2008