slide_sw Project Status | |||
Project File: | slide_sw.ise | Current State: | Programming File Generated |
Module Name: | slide_to_led |
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No Errors |
Target Device: | xc3s700a-4fg484 |
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No Warnings |
Product Version: | ISE 10.1.01 - WebPACK |
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All Signals Completely Routed |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
slide_sw Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Logic Distribution | |||||
Number of Slices containing only related logic | 0 | 0 | 0% | ||
Number of Slices containing unrelated logic | 0 | 0 | 0% | ||
Number of bonded IOBs | 8 | 372 | 2% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Thu Jun 12 10:41:56 2008 | 0 | 0 | 0 | |
Translation Report | Current | Thu Jun 12 10:42:08 2008 | 0 | 0 | 0 | |
Map Report | Current | Thu Jun 12 10:42:11 2008 | 0 | 0 | 4 Infos (0 new, 0 filtered) | |
Place and Route Report | Current | Thu Jun 12 10:42:20 2008 | 0 | 0 | 1 Info (0 new, 0 filtered) | |
Static Timing Report | Current | Thu Jun 12 10:42:23 2008 | 0 | 0 | 3 Infos (0 new, 0 filtered) | |
Bitgen Report | Current | Thu Jun 12 10:42:30 2008 | 0 | 0 | 0 |