led_cntr Project Status | |||
Project File: | led_cntr.ise | Current State: | Programming File Generated |
Module Name: | led_cntr_code |
|
No Errors |
Target Device: | xc3s700a-4fg484 |
|
No Warnings |
Product Version: | ISE 10.1.01 - WebPACK |
|
All Signals Completely Routed |
Design Goal: | Balanced |
|
All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
|
0 (Timing Report) |
led_cntr Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 66 | 11,776 | 1% | ||
Number of 4 input LUTs | 3 | 11,776 | 1% | ||
Logic Distribution | |||||
Number of occupied Slices | 35 | 5,888 | 1% | ||
Number of Slices containing only related logic | 35 | 35 | 100% | ||
Number of Slices containing unrelated logic | 0 | 35 | 0% | ||
Total Number of 4 input LUTs | 66 | 11,776 | 1% | ||
Number used as logic | 3 | ||||
Number used as a route-thru | 63 | ||||
Number of bonded IOBs | 9 | 372 | 2% | ||
Number of BUFGMUXs | 1 | 24 | 4% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Wed Jun 11 16:46:08 2008 | 0 | 0 | 0 | |
Translation Report | Current | Wed Jun 11 16:46:14 2008 | 0 | 0 | 0 | |
Map Report | Current | Wed Jun 11 16:46:18 2008 | 0 | 0 | 4 Infos (0 new, 0 filtered) | |
Place and Route Report | Current | Wed Jun 11 16:46:29 2008 | 0 | 0 | 2 Infos (0 new, 0 filtered) | |
Static Timing Report | Current | Wed Jun 11 16:46:32 2008 | 0 | 0 | 3 Infos (0 new, 0 filtered) | |
Bitgen Report | Current | Wed Jun 11 16:46:42 2008 | 0 | 0 | 0 |