led_cntr Project Status
Project File: led_cntr.ise Current State: Programming File Generated
Module Name: led_cntr_code
  • Errors:
No Errors
Target Device: xc3s700a-4fg484
  • Warnings:
No Warnings
Product Version: ISE 10.1.01 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
led_cntr Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 66 11,776 1%  
Number of 4 input LUTs 3 11,776 1%  
Logic Distribution     
Number of occupied Slices 35 5,888 1%  
    Number of Slices containing only related logic 35 35 100%  
    Number of Slices containing unrelated logic 0 35 0%  
Total Number of 4 input LUTs 66 11,776 1%  
    Number used as logic 3      
    Number used as a route-thru 63      
Number of bonded IOBs 9 372 2%  
Number of BUFGMUXs 1 24 4%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Jun 11 16:46:08 2008000
Translation ReportCurrentWed Jun 11 16:46:14 2008000
Map ReportCurrentWed Jun 11 16:46:18 2008004 Infos (0 new, 0 filtered)
Place and Route ReportCurrentWed Jun 11 16:46:29 2008002 Infos (0 new, 0 filtered)
Static Timing ReportCurrentWed Jun 11 16:46:32 2008003 Infos (0 new, 0 filtered)
Bitgen ReportCurrentWed Jun 11 16:46:42 2008000

Date Generated: 06/11/2008 - 16:52:21