slide_sw Project Status
Project File: slide_sw.ise Current State: Programming File Generated
Module Name: slide_to_led
  • Errors:
No Errors
Target Device: xc3s700a-4fg484
  • Warnings:
No Warnings
Product Version: ISE 10.1.01 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
 
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
slide_sw Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Logic Distribution     
    Number of Slices containing only related logic 0 0 0%  
    Number of Slices containing unrelated logic 0 0 0%  
Number of bonded IOBs 8 372 2%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Jun 12 10:41:56 2008000
Translation ReportCurrentThu Jun 12 10:42:08 2008000
Map ReportCurrentThu Jun 12 10:42:11 2008004 Infos (0 new, 0 filtered)
Place and Route ReportCurrentThu Jun 12 10:42:20 2008001 Info (0 new, 0 filtered)
Static Timing ReportCurrentThu Jun 12 10:42:23 2008003 Infos (0 new, 0 filtered)
Bitgen ReportCurrentThu Jun 12 10:42:30 2008000

Date Generated: 06/12/2008 - 12:21:35